Event

Testing of digital circuits plays a critical role during the design and manufacturing cycles. It also ensures the quality of parts shipped to the customers. Test generation and design for testability are integral parts of automated design flow of all electronic products. The objective of this course is to provide more advanced topics on testing of digital systems and complement the foundation covered in Testing Digital Systems I.

Topics include Functional and Structural Testing (design verification vectors, exhaustive test, pseudo-exhaustive test, pseudo-random testing), Essentials of Test Generation for Sequential Circuits (state-machine initialization, time-frame expansion method), Built-in Self Test (test economics of BIST, test pattern generation, output respone analysis, BIST architectures), Boundry Scan (Boundry scan architectures, BS test methodology), Delay Testing (path delay test, hazard-free, robust, and non-robust delay tests), transition faults, delay test schemes), Current-Based Testing (motivation, test vectores for IDDQ, variations of IDDQ), Memory Test (memory test algorithm, memory BIST, memory repair), and DFT for System-on-Chip.

The objective of this course is to provide more advanced topics on testing of digital systems and complement the foundation covered in Testing Digital Systems I.